On the eleventh (native time), PCI-SIG formally launched the next-generation customary “PCI Express 6.0” for bus interfaces, which doubled the bandwidth of the earlier era.
It achieves a knowledge charge of 64GT / s per lane, which is twice that of the earlier era PCI Express 5.0, and reaches a most switch charge of 256GB / s in 16 lanes. It additionally reduces latency and bandwidth upwards, and maintains backward compatibility with older era requirements.
Utilizes PAM4 (4-Level Pulse Amplitude Modulation), which encrypts 2-bit knowledge at 4 voltage ranges, and Flit (Flow Control Unit) based mostly on encoding expertise. In addition, FEC (Forward Error Correct) and CRC (Cyclic Redundancy Check) suppress bit errors.